The present invention relates to a memory circuit testing system, a semiconductor device, and a memory testing method, and more specifically relates to a memory circuit testing system including a plurality of memory circuits and a testing circuit on the same chip, in which the testing circuit performs function tests of the memory circuits, a semiconductor device, and a memory testing method.
In recent years, semiconductor integrated circuit devices (LSI), such as ASIC (Application Specific IC) and the like, have become capable of having a plurality of large-capacity memory circuits built into a single chip together with logic circuits to attain high integration and high functionality. In such semiconductor devices, the transmission rate (data quantity transmitted per unit time) between the logic circuits and memory circuits is increased more than in conventional semiconductor devices.
Semiconductor devices are subjected to performance testing to test whether or not the logic circuits and memory circuits are operating properly prior to shipping. These logic circuits and memory circuits each include circuits of function block units having a plurality of logic gates. Therefore, the output condition of the semiconductor device when testing specific function block circuits is affected by the condition of function block circuits other than the one being tested. Furthermore, the pace of improvement of the integration of semiconductor devices increases every year, with the number of installed memory circuits increasing in conjunction with the growing multifunctionality of semiconductor devices, thus making the testing of the function blocks of memory circuits in particular very complex.
Accessing and testing memory circuits directly from an external device has been considered as a method for testing a semiconductor device having a plurality of built-in memory circuits. However, the memory circuit has an input/output terminal connected to a logic circuit. This causes problems, such as difficulty in performing memory circuit input/output from outside the semiconductor device, and an increase in the number of testing terminals.
Therefore, in recent years a built-in self test (BIST) means built into a semiconductor device to perform a memory circuit test and output the test result to an external device has been proposed as a means for simplifying function tests of memory circuits built into a semiconductor device.
Generally, when a plurality of memory circuits are built into the same chip, a testing circuit (BIST) is built in on a one-to-one basis for each memory circuit. That is, a testing circuit is provided for each memory circuit to test the memory circuit. This adequately ensures the accuracy for testing each memory circuit.
FIG. 10 is a block diagram showing an example of the connection between a testing circuit and a memory circuit. The example shows a DRAM (dynamic random access memory) as the memory being tested. A clock signal CLK is provided to the testing circuit 10 and the memory circuit (DRAM macro) 11. A test bit (control signal) TB is also input to the testing circuit 10. Accordingly, a plurality of pairs of testing circuits 10 and memory circuits 11 are built into the same chip, and the testing of all the memory circuits 11 is started simultaneously, with each testing circuit 10 determining the test result of the corresponding memory circuit.
The testing circuit 10 outputs a command control signal, an address signal, and write data generated in response to the test bit TB to the corresponding memory circuit 11. In the testing circuit 10, expected value data (not shown in the drawing) read from the memory circuit 11 is generated. Then, a comparator circuit (not shown in the drawing) of the testing circuit 10 compares the expected value data with the read data having cell information read from the memory circuit 11, and outputs a determination signal to the outside of the device.
The DRAM, which is used as memory, performs a data rewrite operation, i.e., a refresh operation at predetermined time intervals to maintain the data written to the DRAM. Accordingly, the refresh operation must be performed within the time during which the data stored in the DRAM is maintained. In the testing circuit 10, a refresh test is conducted as a test for verifying the data holding time in the DRAM or the like that requires the refresh operation.
FIG. 11 is a flow chart illustrating the refresh test.
The refresh test starts when a clock signal CLK is provided to the testing circuits 10 (step S10). This initializes the testing circuits 10 and the memory circuits (DRAM macro) 11 (step S20 and step S30), and write operations are executed to write data to all of the memory circuits 11 (step S40).
When the write operations for writing data to all of the memory cells in step S40 ends, there is a wait state during which access (read operation) from the testing circuit 10 to the memory circuit 11 is prohibited for a predetermined time (step S50). The time during which access to the memory circuits 11 is prohibited, i.e., the wait state (step S50), is set so as to be equal to the data holding time of the memory circuits 11, and the data holding time is equivalent to a refresh test time tREF (refresh interval).
Thereafter, accessing of the memory circuits 11 is resumed, data is read from the memory circuits 11, and then the read data is compared with the expected value data generated by the comparator circuit to determine whether or not the write data of step S40 is held (step S60).
Then, the determination signal is held or output (step S70).
As described above, the refresh test time tREF is realized by prohibiting access to the memory circuit 11 for a predetermined time period, and the two means described below are provided as examples of means for prohibiting such access.
A first means is to prevent the clock signal CLK from being provided to the testing circuit 10. FIG. 12 is a transition chart of the refresh test.
In this method, after the writing of data to the memory circuit 11 in step S40 ends, access to the memory circuit 11 is prohibited by stopping the clock signal CLK from being provided. Then, the access to the memory circuit 11 is resumed and the wait state (step S50) is ended by providing the clock signal CLK again to the testing circuit 10 and the memory circuit 11.
A second means is to generate a wait signal Wait from the test bit TB input to the testing circuit 10 so as to force the testing circuit 10 into the wait state (step S50). FIG. 13 shows a refresh test transition chart for when the wait signal Wait is used as the test bit TB.
In this method, when the writing of data to the memory circuit 11 ends, the testing circuit 10 enters a wait state (step S50) when the wait signal Wait goes high. Thereafter, the testing circuit 10 ends the wait state (step S50) when the wait signal Wait goes low.
FIG. 14 is a flow chart of the wait state (step S50). The operation descriptions in FIG. 14 are based on hardware description language (VHDL: very high speed IC-hardware description language).
When the wait state is entered (step S50), a determination is made in the testing circuit 10 as to whether or not a clock signal CLK is being provided to the testing circuit 10 and the memory circuit 11 (step S51).
Next, in a state in which the clock signal CLK is held, a determination is made as to whether or not the wait signal Wait is high or low (step S52). At this time, when the wait signal Wait is high, the testing state is maintained in the wait state (step S50). However, when the wait signal Wait is low, the wait state (step S50) ends.
Generally, a plurality of memory circuits built into the same chip have address spaces (memory capacity) that differ in size in accordance with the specifications of the built-in logic circuits.
FIG. 15 is a transition chart of the refresh test when two sets of testing circuits 12a and 12b and memory circuits (DRAM macros) 13a and 13b are built into the same chip. The address spaces of the memory circuits 13a and 13b are Na and Nb (Na<Nb), respectively.
When the wait signal Wait goes high at the same time as when the writing to the memory circuit 13a ends, the testing circuit 12a enters the wait state in response to the high wait signal Wait. At this time, since the address space Na and Nb of the memory circuits 13a and 13b are different, there is a difference in the time for writing data to the memory circuits 13a and 13b. That is, the writing operation to the memory circuit 13b is performed continuously.
Next, when the writing to the memory circuit 13b ends, the testing circuit 12b enters the wait state in response to the high wait signal Wait.
Subsequently, the wait states of the testing circuits 12a and 12b end simultaneously when the wait signal Wait goes low after a refresh test time tREF-b of the memory circuit 13b elapses. Accordingly, the refresh test time tREF-a of the memory circuit 13a is longer than the refresh test time tREF-b of the memory circuit 13b. 
Since the memory circuits 13a and 13b have the same cell configuration, they have the same data holding time. Accordingly, both testing circuits 12a and 12b must have the same refresh test time during which the testing circuits 12a and 12b waits.
When, however, the address spaces Na and Nb of the memory circuits 13a and 13b are different (Na<Nb) as described above, and the basic cycle time for the refresh test time of the testing circuits 12a and 12b is represented by Rc, a time difference is generated in the writing times ((Nb−Na)*Rc).
Accordingly, in the conventional testing circuits 12a and 12b, the refresh test time tREF-a of the memory circuit 13a becomes excessive by time ((Nb−Na)*Rc) from the refresh test time tREF-b of the memory circuit 13b. Therefore, a problem arises inasmuch as the data holding time of the memory circuit 13a cannot be confirmed.
It is an object of the present invention to provide a memory circuit testing system capable of realizing a refresh test of a plurality of memories built into the same chip via a common control signal, and to prevent excessive refresh testing.